The present invention relates to a virtual memory computer system and more particularly to a method and apparatus for providing access to a virtual address whose data is currently located in main memory. The present invention can access the virtually addressed data which is currently located in main memory in the same amount of time that is required to access a real address.
The cost of memory hardware practically limits the amount of semiconductor RAM that can be used in a data processing system. However, data processing system users continue to demand greater memory capabilities from their systems than can be supported by the practical amount of semiconductor RAM. This user demand for greater capabilities has made virtual memory computer systems very popular. Such systems make the relatively inexpensive storage space of a disk or similar mass storage device appear to the rest of the system to be a very large semiconductor RAM address space. Accesses to the virtual memory addresses are processed by the operating system such that they are `transparent` to the user. Thus, virtual memory systems provide a user friendly supplement to the semiconductor RAM main memory in a data processing system.
In known data processing systems, the advantages in cost and user friendliness of virtual systems must, however, be balanced against the typically considerable disadvantage in processing speed experienced during a virtual memory address access. A good discussion of the access problem of known virtual systems is found in U.S. Pat. No. 4,737,909 issued Apr. 12, 1988 to Harada entitled CACHE MEMORY ADDRESS APPARATUS, which is hereby incorporated by reference. In these known systems, extra processing cycles are added to each virtual memory access which requires the translation of a virtual memory address into a real memory address in order for further processing to take place. These known systems all use the common solution of storing the previously translated virtual addresses and their respective real addresses in a large lookup table. Such an approach does not save processing time the first time each virtual address therein is translated to a corresponding real address, but it does save processing time on subsequent accesses to any virtual address already in the table, as long as the lookup time is less than the translation time.
The translation delay and the lookup delay of a lookup table provide major speed disadvantages in RISC and similar systems, where the goal is to perform each instruction in one machine cycle. This is especially true if the system is performing an access to a virtual memory address using a variable offset from a fixed memory location. In the offset addressing mode, which is a common one, the offset value, which is contained in the offset address instruction, must be added to a base address in order to obtain a virtual address, and subsequently the virtual address must be translated to a real address. In such a mode, the known virtual systems would take the time to add the offset to the base address and then take more time to do either a translation or a lookup of the virtual address. The cumulative time delay produced in any of the known systems would be very undesirable in a RISC or similar system. Moreover, if the system were a pipelined system, as most RISC systems are, the pipeline would be held up for the completion of each translation/lookup of a virtual memory address, thereby reducing the advantages of a pipeline data processing system.
It is an object of the present invention to provide a virtual memory address system that divides the conversion of a virtual address to a real address into a number of operations and subsequently processes these operations in parallel to increase processing speed.
It is another object of this invention to provide a pipelined virtual memory system that converts a virtual address to a real address in operations which are performed in parallel with the advancing of the pipeline stages, in order to speed up virtual accesses.
It is further object of this invention to provide a pipelined system for offset addressing to a virtual address wherein the conversion to a real address is processed in parallel with the advancing of the pipeline stages in order to speed up offset accesses.